SPARC M7 Processor and Product Overview Assessment

1.  Which statement is true? 

 The S4 supports 16 threads per core

The SPARC M7 processor uses the fourth generation CMT Core, referred to as S4 (*)      

The SPARC M7 processor uses the fourth generation CMT Core, referred to as S3.

The S3 supports 16 threads per core

2.  How does the M7 processor implement SSM within its silicon? 

By improving the crytography performance within the M7 processor chip

By implementing 8 DAX units to function as co-processors (*)

By increasing the size of the instruction pipeline  

By implementing increasing the cache size

 

3.  How many virtual CPUs can the M7 support considering that each thread can be a virtual CPU? 

32

64  

128

256 (*)

 

4.  Which response is the definition of a DAX?    

(Choose all correct answers)

A co-processor chip that offloads the data compression and decompression functions from the software threads      

A co-processor with the M7 processor that offloads the data compression and decompression functions from the software threads (*)      

A memory control unit within the M7 processor

A memory control unit chip outside of the M7 processor (*)

  

5.  Which two features are part of the SPARC M7 processor’s power management features? 

(Choose all correct answers)

Dynamic Voltage Frequency Scaling (*)  

Dynamic memory allocation

Voltage Acclimatization  

power gating (*)

6.  Which systems use the SPARC M7 processor?        

(Choose all correct answers)

SPARC M6-32

SPARC T7-2 (*)

Oracle SuperCluster T5-8

SPARC T7-4 (*)

Oracle SuperCluster M7 (*)  

    

7.  Which is the function of the Mystic River ASIC? 

Memory Buffer

I/O Hub (*)

Service Processor

Disk Controller

  

8.  Which type of DIMMs are supported by the M7 processor? 

DDR5

DDR4 (*)

DDR3

 DDR2

9.  How many layers of cache does the SPARC M7 processor have? 

 1

 2

 3

 4 (*)

  

10.  Which three statements are true about M7 processors?         

(Choose all correct answers)  

Each M7 processor provides coherency links, referred to as CLINKs (*)

CLINKS are used on both the M7 and T7 servers (*)

Level 4 cache is one of the most important processor enhancements  

CLINKS provide for inter-processor connections (*)

SSM is also a common features with Intel Processors

11.  Which two responses are true about the SPARC M7-8 Server? 

 (Choose all correct answers)  

The M7-8 has a maximum of 4 processors

The M7-8 with 2 PDOM is configured as a 2x4 socket arrangement with a maximum of 8 processors (*)      

The M7-8 with 2 PDOM is configured as a 1x8 socket arrangement with a maximum of 8 processors       The M7-8 with 1 PDOM has cache coherency between all 8 M7 processors (*)

The M7-8 with 1 PDOM uses the same internal interconnects as that of the M7-8 with 2 PDOM  

12.  Which interconnect is common to the M7-8 and M7-16 configurations? 

II_W_248

II_8_N_RO

II_CMIOU_SP (*)

XI_N_4_T2B_S

13.  How many DIMM slots are supported on each CMIOU? 

8

16 (*)

32

 64   

14.  What is the Silicon Secured Memory feature? 

A "Software in Silicon" feature where a DAX used to accelerate data decompression by offloading it from the software threads.      

A "Software in Silicon" feature where DAX used to execute the database queries offloading it from the software threads.      

A "Software in Silicon" feature that improves the performance of Java.

A "Software in Silicon" feature that adds a 16 bit application data bits which can associate the pointer to the object it is pointing to. (*)  

15.  Select the two specifications that correspond to the M7 processor?   

(Choose all correct answers)       

Total of 3 memory controllers

Greater than a 4.0 GHz clock speed (*)

Total of 32 cores (*)

Total of 512KB level 2 data cache per core pair

Total of 4 MB of level 3 cache per each set of 4 cores

16.  Which are the boot options available on the SPARC M7-8 and M7-16 Servers?   

(Choose all correct answers)

Versaboot/eUSB (*)

Internal HBA and HDD

USB port for a flash stick

Aura3 Memory Express (NVMe) controller and a Solid-State Disk (SSD). (*)

16 Gb FC to FC SAN attached Storage using Ganymede-Q or Ganymede-E (*)

17.  How many CMIOUs are there in a DCU in the M7-16? 

1

2

3

4 (*)    

18.  Which features of “Software in Silicon” are supported by the SPARC M7 processor?        

(Choose all correct answers)

Database Query Acceleration (*)

Database Decompression (*)

 Silicon Secured Memory (*)

 scalability links

 coherency links

19.  How many M7 processors are supported on each CMIOU? 

1 (*)

2

3

4

20.  Which links are connected to the switch units from the CMIOUs on the M7-16? 

coherency

scalability (*)

cache  

memory